A solid state drive (SSD) is a data storage device that utilizes solid-state memory to retain data in nonvolatile memory chips. NAND-based flash memories are widely used as the solid-state memory storage in SSDs due to their compactness, low power consumption, low cost, high data throughput and reliability. SSDs commonly employ several NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
While NAND-based flash memories are reliable, they are not inherently error-free and often rely on error correction coding (ECC) to correct raw bit errors in the stored data. One commonly employed error correction code employed in nonvolatile memory storage modules, such as SSDs, are low-density parity-check (LDPC) codes. An LDPC code is a linear error correcting code having a parity check matrix with a small number of nonzero elements in each row and column.
Various methods for decoding data encoded with LDPC error correction codes are known in the art, including the sum-product algorithm (SPA) and the min-sum algorithm (MSA). While the sum-product algorithm (SPA) is known to achieve the best decoding performance, it is computationally complex. The min-sum algorithm (MSA) was introduced to reduce the computationally complexity inherent in the sum-product algorithm. Additionally, one commonly employed decoding method for LDPC coding is the layered min-sum algorithm (MSA). The layered min-sum algorithm is iterative by layer of the parity check matrix.
The decoding of LDPC encoded data, when utilizing either the sum-product algorithm or the min-sum algorithm, requires the maintenance and storage of a large amount of data that is iteratively passed between the check nodes and the variable nodes during the decoding process. The memory storage requirements to store the variables, such as random access memory (RAM), may be very large and as such, may require a significant amount of space on the integrated circuit. In addition to the memory storage requirements, the associated logic required for routing the data between the variable nodes and the check nodes and the processing engines of the variable nodes and the check nodes consume valuable space on the integrated circuit device. It desirable to reduce the amount of space required for the memory storage and also to reduce the hardware required for the routing of data between the variable nodes and the check nodes.
Accordingly, what is needed in the art is an improved system and method that reduces the memory storage requirements for iterative decoding methods, such as LDPC decoding.